an array of memory cells organized into NAND strings,

each memory cell being a charge storage transistor having a source and drain, a charge storage element and a control gate,

each NAND string having a source end and a drain end and being formed by a series of charge storage transistors daisy-chained by the drain of one cell to the source of the adjacent charge storage transistor and switchable to the source end by a source select transistor and switchable to the drain end by a drain select transistor, and wherein:

each NAND string consists of a first group and a second group of memory cells, with the second group of memory cells being adjacent to either the source select transistor or the drain select transistor and the first group of memory cells being the complement of the second group in the NAND string;

means for storing in each memory cell of the first group a first predetermined number of bits of data; and

means for storing in each memory cell of the second group a second predetermined number of bits of data less than the first predetermined number.