| US 7,489,547 B2 | ||
| Method of NAND flash memory cell array with adaptive memory state partitioning | ||
| Farookh Moogat, Fremont, Calif. (US); and Teruhiko Kamei, Yokohama (Japan) | ||
| Assigned to Sandisk Corporation, Milpitas, Calif. (US) | ||
| Filed on Dec. 29, 2006, as Appl. No. 11/618,482. | ||
| Prior Publication US 2008/0158968 A1, Jul. 03, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—185.17 [365/185.18; 365/185.03] | 22 Claims |
| 1. In a non-volatile memory having an array of memory cells organized into NAND strings, each memory cell being a charge storage
transistor having a source and drain, a charge storage element and a control gate, each NAND string having a source end and
a drain end and being formed by a series of charge storage transistors daisy-chained by the drain of one cells to the source
of the adjacent charge storage transistor and switchable to the source end by a source select transistor and switchable to
the drain end by a drain select transistor, a method of storing data in the non-volatile memory, comprising:
distinguishing the memory cells of each NAND string into a first group and a second group, the memory cells of the second
group being adjacent to either the source select transistor or the drain select transistor and the memory cells of the first
group being the complement of the second group;
storing in each memory cell of the first group a first predetermined number of bits of data; and
storing in each memory cell of the second group a second predetermined number of bits of data less than the first predetermined
number.
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