| US 7,489,204 B2 | ||
| Method and structure for chip-level testing of wire delay independent of silicon delay | ||
| Peter A. Habitz, Hinesburg, Vt. (US); and Anthony D. Polson, Jericho, Vt. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Jun. 30, 2005, as Appl. No. 11/160,603. | ||
| Prior Publication US 2007/0001682 A1, Jan. 04, 2007 | ||
| Int. Cl. G01R 23/00 (2006.01); H03B 5/24 (2006.01); H03K 3/03 (2006.01) | ||
| U.S. Cl. 331—44 [331/57] | 20 Claims |
| 1. An integrated circuit testing structure comprising:
a tester comprising:
a multiplexer in a metal layer of a semiconductor chip;
a ring oscillator in said metal layer electrically connected to said multiplexer;
a first wire in said metal layer electrically connected to said multiplexer; and
a second wire in said metal layer electrically connected to said multiplexer,
wherein said first wire is longer than said second wire, and
wherein said multiplexer is adapted to selectively connect said ring oscillator to one of said first wire and said second
wire;
a monitor electrically connected to said ring oscillator and adapted to measure a first ring frequency of said ring oscillator,
when said ring oscillator is connected to said first wire, and a second ring frequency of said ring oscillator, when said
ring oscillator is connected to said second wire; and
a processor in communication with said monitor and adapted to determine a resistance-capacitance delay of said metal layer
based upon a difference between said first ring frequency and said second ring frequency.
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