| US 7,489,173 B1 | ||
| Signal adjustment for duty cycle control | ||
| Himanshu J. Verma, Mountain View, Calif. (US); and Kwansuhk Oh, San Jose, Calif. (US) | ||
| Assigned to Xilinx, Inc., San Jose, Calif. (US) | ||
| Filed on Feb. 18, 2005, as Appl. No. 11/61,697. | ||
| Int. Cl. H03K 3/017 (2006.01); H03K 9/08 (2006.01); G01R 29/02 (2006.01) | ||
| U.S. Cl. 327—175 [327/35; 327/38; 327/176] | 20 Claims |
| 1. A method for providing a duty cycle adjusted signal, comprising:
providing a first sample clock signal;
providing a second sample clock signal;
generating a first phase signal and a second phase signal responsive to the first sample clock signal, the first phase signal
being out of phase with respect to the second phase signal;
generating a combined signal, the combined signal having a duty cycle associated with the first phase signal and the second
phase signal in combination;
clocking a first counter to provide a first count, the first counter clocked with the second sample clock signal;
clocking a second counter to provide a second count, the second counter clocked with the second sample clock signal;
periodically activating and deactivating the first counter responsive to the combined signal to affect the first count;
maintaining the second counter in an active state for counting; and
dividing the first count from the first counter with the second count from the second counter to obtain the duty cycle associated
with the combined signal.
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