| US 7,489,163 B2 | ||
| FPGA powerup to known functional state | ||
| Kenneth J. Goodnow, Essex Junction, Vt. (US); Clarence R. Ogilvie, Huntington, Vt. (US); Christopher B. Reynolds, Milton, Vt. (US); Jack R. Smith, South Burlington, Vt. (US); Sebastian T. Ventrone, South Burlington, Vt. (US); and Keith R. Williams, Essex Junction, Vt. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Oct. 10, 2007, as Appl. No. 11/869,921. | ||
| Application 11/869921 is a continuation of application No. 11/162997, filed on Sep. 30, 2005, granted, now 7,282,949. | ||
| Prior Publication US 2008/0030226 A1, Feb. 07, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06F 7/38 (2006.01); H03K 19/177 (2006.01) | ||
| U.S. Cl. 326—38 [326/39; 326/40] | 9 Claims |
| 1. A field programmable gate array (FPGA) device comprising:
a non-non-programming-based default power-on electronic configuration defining a default state to initial a first logic function,
wherein the non-non-programming-based default power-on electronic configuration is one of a mask via circuit, an asynchronous
set/reset circuit, an unbalanced latch circuit, or a flush scan circuit.
|