US 7,489,021 B2
Lead frame with included passive devices
Frank J. Juskey, Apopka, Fla. (US); Daniel K. Lau, San Francisco, Calif. (US); and Lawrence R. Thompson, San Jose, Calif. (US)
Assigned to Advanced Interconnect Technologies Limited, Port Louis (Mauritius)
Appl. No. 10/563,172
PCT Filed Feb. 17, 2004, PCT No. PCT/US2004/004676
§ 371(c)(1), (2), (4) Date Jun. 08, 2007,
PCT Pub. No. WO2004/077508, PCT Pub. Date Sep. 10, 2004.
Claims priority of provisional application 60/449049, filed on Feb. 21, 2003.
Prior Publication US 2008/0036034 A1, Feb. 14, 2008
Int. Cl. H01L 23/495 (2006.01); H01L 23/34 (2006.01); H01L 21/00 (2006.01)
U.S. Cl. 257—666  [257/676; 257/684; 257/693; 257/698; 257/723; 257/924; 438/106; 438/123; 438/51; 438/54; 438/108] 35 Claims
OG exemplary drawing
 
1. A semiconductor device package (10) configured for electrical connection to an external circuit, the semiconductor device package (10) comprising:
a package body (30);
a semiconductor device (12) disposed within the package body (30);
at least one passive device (14) disposed within the package body (30); and
a lead frame (17) formed from electrically conductive material, the lead frame (17) including:
a plurality of leads (16) electrically connected to I/O pads (22) on the semiconductor device (12), each of the leads (16) including a first surface (38) exposed from the package body (30) for electrical connection to the external circuit, and
a plurality of first interposers (20) electrically connected to the at least one passive device (14), at least one interposer (20) in the plurality of interposers (20) being electrically connected to at least one lead (16) in the plurality of leads (16) for electrically connecting the at least one passive device (14) with the external circuit,
wherein at least one of the first interposers (20) in the plurality of first interposers (20) includes a support post (58) extending therefrom, the support post (58) being exposed at a surface (34) of the package body (10).