| US 7,489,018 B2 | ||
| Transistor | ||
| Mitsuhiko Kitagawa, Tokyo (Japan); Takashi Nishimura, Hyogo-ken (Japan); Yusuke Kawaguchi, Kanagawa-ken (Japan); and Syotaro Ono, Kanagawa-ken (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Minato-ku, Tokyo (Japan) | ||
| Filed on Apr. 18, 2006, as Appl. No. 11/405,672. | ||
| Claims priority of application No. 2005-121237 (JP), filed on Apr. 19, 2005; and application No. 2006-109949 (JP), filed on Apr. 12, 2006. | ||
| Prior Publication US 2006/0231894 A1, Oct. 19, 2006 | ||
| Int. Cl. H01L 27/082 (2006.01); H01L 27/102 (2006.01); H01L 29/70 (2006.01); H01L 31/11 (2006.01) | ||
| U.S. Cl. 257—578 [257/211; 438/270] | 20 Claims |
| 1. A transistor comprising:
an insulating layer;
a semiconductor layer provided on a major surface of the insulating layer, the semiconductor layer having
a source portion having a plurality of source regions of a first conductivity type and a plurality of base contact regions
of a second conductivity type, the source regions being alternated with the base contact regions,
a drain portion of the first conductivity type, and
a base region of the second conductivity type provided between the source portion and the drain portion, the base region being
in contact with the source regions and the base contact regions;
a gate insulating layer provided on the base region; and
a gate electrode provided on the gate insulating layer,
a distance between the source regions and the drain portion being smaller than a distance between the base contact regions
and the drain portion.
|