US 7,489,016 B2
Trench-constrained isolation diffusion for integrated circuit die
Richard K. Williams, Cupertino, Calif. (US); Michael E. Cornell, Campbell, Calif. (US); and Wai Tien Chan, Hong Kong (China)
Assigned to Advanced Analogic Technologies, Inc., Santa Clara, Calif. (US); and Advanced Analogic Technologies (Hong Kong) Limited, Hong Kong (China)
Filed on Aug. 15, 2005, as Appl. No. 11/204,215.
Application 11/204215 is a division of application No. 10/218678, filed on Aug. 14, 2002, granted, now 6,943,426.
Prior Publication US 2005/0272207 A1, Dec. 08, 2005
Int. Cl. H01L 23/58 (2006.01)
U.S. Cl. 257—500 15 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a semiconductor substrate of a first conductivity type;
an epitaxial layer of said first conductivity type formed over said substrate;
a trench formed in said epitaxial layer, said trench having a bottom in said epitaxial layer above an interface between said epitaxial layer and said substrate, said trench containing a dielectric material;
a region of a second conductivity type abutting a side of said trench;
a second trench formed in said epitaxial layer, said second trench having a bottom in said epitaxial layer above said interface between said epitaxial layer and said substrate, said second trench containing a dielectric material, said region abutting a side of said second trench; and
a buried layer of said second conductivity type, said buried layer extending upward from said substrate and merging with said region.