| US 7,488,678 B2 | ||
| Method of manufacturing interconnect substrate | ||
| Satoshi Kimura, Fujimi (Japan); Hidemichi Furihata, Chino (Japan); and Toshihiko Kaneda, Chino (Japan) | ||
| Assigned to Seiko Epson Corporation, (Japan) | ||
| Filed on Mar. 09, 2007, as Appl. No. 11/716,720. | ||
| Claims priority of application No. 2006-065988 (JP), filed on Mar. 10, 2006. | ||
| Prior Publication US 2007/0212871 A1, Sep. 13, 2007 | ||
| Int. Cl. H01L 21/4763 (2006.01) | ||
| U.S. Cl. 438—618 [438/678; 257/E21.59; 257/E21.487; 257/E21.492] | 11 Claims |
| 1. A method of manufacturing an interconnect substrate by electroless plating, the method comprising:
(a) forming a catalyst layer with a specific pattern on a substrate;
(b) immersing the substrate in a first electroless plating solution including a first metal to deposit the first metal on
the catalyst layer to form a first metal layer; and
(c) immersing the substrate in a second electroless plating solution including a second metal to deposit the second metal
on the first metal layer to form a second metal layer,
an ionization tendency of the first metal being higher than an ionization tendency of the second metal.
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