| US 7,488,668 B2 | ||
| Manufacturing method for semiconductor devices, arrangement determination method and apparatus for semiconductor device formation regions, and program for determining arrangement of semiconductor device formation regions | ||
| Kiyoshi Arita, Fukuoka-ken (Japan); Hiroshi Haji, Fukuoka-ken (Japan); Kazuhiro Noda, Fukuoka-ken (Japan); Akira Nakagawa, Saga-ken (Japan); and Teruaki Nishinaka, Saga-ken (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Jul. 19, 2005, as Appl. No. 11/183,739. | ||
| Claims priority of application No. 2004-215364 (JP), filed on Jul. 23, 2004. | ||
| Prior Publication US 2006/0019416 A1, Jan. 26, 2006 | ||
| Int. Cl. H01L 21/00 (2006.01); H01L 23/544 (2006.01) | ||
| U.S. Cl. 438—460 [438/14; 257/620; 257/E21.599; 257/E23.179] | 24 Claims |
| 1. A manufacturing method for semiconductor devices, which is a method for determining an arrangement of a plurality of unit-device-formation-regions
that are rectangular regions for forming the semiconductor devices in a device-formation-effective-region on a semiconductor
wafer and manufacturing the semiconductor devices based on the determined arrangement, the method comprising:
forming a plurality of parallel-line-partition-regions partitioned by an outer periphery of the device-formation-effective-region
on the wafer and a plurality of parallel lines, by disposing the respective parallel lines in the device-formation-effective-region
on the wafer with use of a length-dimension of a second-line-segment out of a first-line-segment and the second-line-segment
which constitute the unit-device-formation-region and are orthogonal to each other as an arrangement interval, through execution
of computer processing;
forming one or a plurality of the unit-device-formation-regions partitioned by the respective parallel lines and a plurality
of the second-line-segments in the parallel-line-partition-regions, by disposing the respective second-line-segments in a
direction orthogonal to the parallel lines in the respective parallel-line-partition-regions with use of a length-dimension
of the first-line-segment as an arrangement interval, through execution of computer processing;
determining an arrangement of the unit-device-formation-regions which maximizes each number of the unit-device-formation-regions
formed in each of the respective parallel-line-partition-regions independently of other parallel-line-partition-regions as
an arrangement of the respective unit-device-formation-regions in the entire device-formation-effective-region on the wafer,
through execution of computer processing, and thereby preparing the determined arrangement as an arrangement information for
the unit-device-formation-regions;
forming the respective semiconductor devices on the semiconductor wafer based on the prepared arrangement information; and
performing a plasma etching process to the semiconductor wafer with a mask disposed thereon from a masked surface to divide
the semiconductor wafer into the respective semiconductor devices in accordance with the arrangement information, and thereby
the respective divided semiconductor devices are manufactured.
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