US 7,488,666 B2
Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device
Kei Kanemoto, Fujimi-cho (Japan)
Assigned to Seiko Epson Corporation, Tokyo (Japan)
Filed on Nov. 29, 2006, as Appl. No. 11/605,606.
Claims priority of application No. 2005-358581 (JP), filed on Dec. 13, 2005.
Prior Publication US 2007/0132025 A1, Jun. 14, 2007
Int. Cl. H01L 21/302 (2006.01); H01L 21/461 (2006.01)
U.S. Cl. 438—424  [438/149; 438/425; 438/427; 438/739; 257/E21.115; 257/E21.116] 3 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor substrate, comprising:
forming a silicon on insulator (SOI) area and an element isolation film on a semiconductor base;
forming a first semiconductor layer on the semiconductor base in the SOI structure area;
forming a second semiconductor layer having an etching selection ratio smaller than an etching selection ratio of the first semiconductor layer on the first semiconductor layer;
removing a part of the second semiconductor layer and a part of the first semiconductor layer in the SOI structure area so as to form a recess exposing the semiconductor base and supporting a support;
forming a support forming layer on the semiconductor base so as to bury the recess and cover the second semiconductor layer;
etching an area excluding the recess, an element area, and an area covering the element isolation film so as to form the support and an opening face exposing a part of end parts of the first semiconductor layer and the second semiconductor layer, the opening face being positioned under the support;
removing the first semiconductor layer and the second semiconductor layer that are disposed at a border between the element isolation film and the SOI structure area and in a vicinity of the border;
etching the first semiconductor layer through the opening face so as to form a cavity between the second semiconductor layer and the semiconductor base;
forming a buried insulation layer in the cavity;
forming an insulation film above the second semiconductor layer; and
planarizing above the second semiconductor layer so as to remove a part of the support.