US 7,488,646 B2
Nonvolatile semiconductor memory device and its manufacturing method
Tadashi Iguchi, Yokkaichi (Japan); Yoshiaki Himeno, Yokkaichi (Japan); and Hiroaki Tsunoda, Yokkaichi (Japan)
Assigned to Kabushiki Kaisha Toshiba, Kawasaki-shi (Japan)
Filed on Mar. 13, 2007, as Appl. No. 11/685,282.
Application 11/094467 is a division of application No. 10/716556, filed on Nov. 20, 2003, granted, now 6,974,746.
Application 10/716556 is a division of application No. 09/732723, filed on Dec. 11, 2000, granted, now 6,720,610.
Application 11/685282 is a continuation of application No. 11/094467, filed on Mar. 31, 2005, granted, now 7,382,015.
Claims priority of application No. 11-350841 (JP), filed on Dec. 09, 1999.
Prior Publication US 2007/0166919 A1, Jul. 19, 2007
Int. Cl. H01L 21/336 (2006.01)
U.S. Cl. 438—257  [438/266] 9 Claims
OG exemplary drawing
 
1. A method for manufacturing a nonvolatile semiconductor memory device, comprising:
forming a first insulating film on a semiconductor substrate having a first upper surface;
forming a first electrode material film on the first insulating film;
etching the first electrode material, the first insulating film, and the semiconductor substrate so as to form a groove in the semiconductor substrate;
embedding a second insulating film in the groove and forming an isolation portion so that an upper portion of the isolation portion protrudes from the first upper surface;
forming a second electrode material film on the first electrode material and the isolation portion;
etching the second electrode material film and the upper portion of the isolation portion so that a pair of inner side surfaces of the isolation portion face to a whole side surface of the first electrode material film via the isolation portion;
forming a third insulating film on the second electrode material film and the pair of inner side surfaces of the isolation portion; and
forming a control gate on the third insulating film and between the pair of inner side surfaces of the isolation portion.