| US 7,487,581 B2 | ||
| Method of manufacturing an inverter device | ||
| Toshiharu Obu, Kanagawa-ken (Japan); Nobumitsu Tada, Tokyo (Japan); Hiroki Sekiya, Kanagawa-ken (Japan); Keizo Hagiwara, Tokyo (Japan); and Shimpei Yoshioka, Kanagawa-ken (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Mar. 22, 2007, as Appl. No. 11/723,826. | ||
| Application 11/723826 is a division of application No. 10/813444, filed on Mar. 21, 2004, granted, now 7,206,205. | ||
| Claims priority of application No. 2003-321462 (JP), filed on Sep. 12, 2003. | ||
| Prior Publication US 2007/0165383 A1, Jul. 19, 2007 | ||
| Int. Cl. H01F 7/06 (2006.01) | ||
| U.S. Cl. 29—602.1 [29/592.1; 29/740; 29/741; 29/759; 29/832; 219/68; 219/70; 361/704; 361/707; 361/717; 363/141; 363/144] | 4 Claims |
| 1. A method of manufacturing an inverter device that includes a plurality of heat buffer plates, comprising:
bonding a plurality of semiconductor chips and said heat buffer plates by a low melting point or high melting point solder;
bonding said heat buffer plates and a conductor by a low melting point or high melting point solder;
dividing a wide conductor into a plurality of chips fixing said conductor to a cooler;
fixing said heat buffer plates with said plurality of chips;
fixing said conductor and said cooler by application of pressure at locations where the plurality of semiconductor chips are
not bonded to said conductor;
forming said conductor as an upper arm conductor and a lower arm conductor; and
bonding a first subset of said heat buffer plates onto said upper arm conductor and bonding a second subset of said heat buffer
plates onto said lower arm conductor.
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