| US 7,487,474 B2 | ||
| Designing an integrated circuit to improve yield using a variant design element | ||
| Dennis Ciplickas, San Jose, Calif. (US); Joe Davis, Unterschleissheim (Germany); Christopher Hess, San Ramon, Calif. (US); Sherry Lee, San Jose, Calif. (US); Enrico Malavasi, Mountain View, Calif. (US); Abdulmobeen Mohammad, Sunnyvale, Calif. (US); Ratibor Radojcic, San Diego, Calif. (US); Brian Stine, Los Altos Hills, Calif. (US); Rakesh Vallishayee, San Jose, Calif. (US); Stefano Zanella, San Jose, Calif. (US); Nicola Dragone, Vobarno (Italy); Carlo Guardiani, Verona (Italy); Michel Quarantelli, Noceto (Italy); Stefano Tonello, Breganze (Italy); and Joshi Aniruddha, Irvine, Calif. (US) | ||
| Assigned to PDF Solutions, Inc., San Jose, Calif. (US) | ||
| Appl. No. 10/541,076 PCT Filed Nov. 17, 2003, PCT No. PCT/US03/37046 § 371(c)(1), (2), (4) Date Jun. 29, 2005, PCT Pub. No. WO2004/061898, PCT Pub. Date Jul. 22, 2004. |
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| Claims priority of provisional application 60/437922, filed on Jan. 02, 2003. | ||
| Prior Publication US 2006/0101355 A1, May 11, 2006 | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—2 [716/4; 716/5; 716/19; 716/20; 716/21] | 64 Claims |
| 1. A method of designing an integrated circuit to improve yield when manufacturing the integrated circuit, the method comprising:
obtaining a design element from a set of design elements used in designing integrated circuits;
creating a variant design element based on the obtained design element, wherein a feature of the obtained design element is
modified to create the variant design element;
determining a yield to area ratio for the variant design element;
if the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element,
retaining the variant design element to be used in designing the integrated circuit, wherein the design element is a bit cell,
the set of design elements is a set of bit cells, and the variant design element is a variant bit cell; and
selecting a memory macro from a set of memory macros; and
applying the variant bit cell to the selected memory macro.
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