| US 7,487,421 B2 | ||
| Emulation cache access for tag view reads | ||
| Raguram Damodaran, Plano, Tex. (US); and Ananthakrishnan Ramamurti, Irvine, Calif. (US) | ||
| Assigned to Texas Instruments Incorporated, Dallas, Tex. (US) | ||
| Filed on Jun. 07, 2006, as Appl. No. 11/422,740. | ||
| Claims priority of provisional application 60/688973, filed on Jun. 09, 2005. | ||
| Prior Publication US 2007/0033470 A1, Feb. 08, 2007 | ||
| Int. Cl. G01R 31/28 (2006.01) | ||
| U.S. Cl. 714—733 [714/30; 714/42; 714/724; 714/718; 365/201] | 5 Claims |
| 1. An integrated circuit comprising:
a plurality of operational circuits to be tested;
a cache memory including a plurality of cache entries storing cached data and corresponding tag bits indicative of cache state
and address cached;
a test read only memory storing at least one test set consisting of a test algorithm and test data;
an external interface; and
a programmable built-in self test unit connected to said plurality of operational circuits to be tested, said test read only
memory and said external interface, said programmable built-is self test unit operable to
load from said test read only memory for each test set stored in said test read only memory one of said test algorithm and
said test data,
test at least one of said plurality of operational circuits to be tested according to said one of said test algorithm and
said test data loaded, and
read tag bits of a predetermined cache entry and output said tag bits via said external interface.
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