| US 7,487,415 B1 | ||
| Memory circuitry with data validation | ||
| Philip Pan, Fremont, Calif. (US) | ||
| Assigned to Altera Corporation, San Jose, Calif. (US) | ||
| Filed on Oct. 01, 2004, as Appl. No. 10/956,984. | ||
| Int. Cl. G01R 31/28 (2006.01) | ||
| U.S. Cl. 714—724 [714/725; 714/718] | 18 Claims |
| 1. Programmable logic device circuitry comprising:
programmable logic circuitry;
memory circuitry;
programmable interconnect circuitry usable to convey signals between the programmable logic circuitry and the memory circuitry;
and
data validation circuitry associated with the memory circuitry for performing a parallel comparison of plural bits of a data
word output by the memory circuitry and applied to the data validation circuitry in parallel to plural bits of another data
word also applied to the data validation circuitry in parallel without having to pass the data word output by the memory circuitry
through the programmable interconnect circuitry.
|