| US 7,487,369 B1 | ||
| Low-power cache system and method | ||
| Mayank Gupta, Sunnyvale, Calif. (US); Edward T. Pak, Saratoga, Calif. (US); Javier Villagomez, San Jose, Calif. (US); and Peter H. Voss, Aromas, Calif. (US) | ||
| Assigned to RMI Corporation, Cupertino, Calif. (US) | ||
| Filed on May 01, 2000, as Appl. No. 9/562,071. | ||
| Int. Cl. G06F 1/32 (2006.01); G06F 12/00 (2006.01) | ||
| U.S. Cl. 713—300 [711/118] | 19 Claims |
| 1. A scalable pipelined cache architecture with at least a first one-way of associativity, comprising:
a first tag array, a first data array and a first address decoder shared by both the first tag array and the first data array,
the first address decoder having an input for receiving the index address, and having an output coupled directly to the first
tag array;
during a first time unit, said first tag array being powered-up for finding a first tag that corresponds to a received index
address;
a first comparator, coupled to said tag array, for comparing the first tag and a tag compare data;
during a later second time unit, said first data array coupled to said first tag array, being powered-up if the output from
said first comparator indicates that there is a tag hit;
wherein said first data array contains data which corresponds to the first tag index address.
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