| US 7,487,281 B2 | ||
| Computer system to control the data transfer between a memory and a peripheral device connected to a CPU via a bus | ||
| Kazuki Okamoto, Hamamatsu (Japan); and Tomohiro Suzuki, Hamamatsu (Japan) | ||
| Assigned to Yamaha Corporation, Hamamatsu-shi (Japan) | ||
| Appl. No. 11/661,526 PCT Filed Nov. 30, 2005, PCT No. PCT/JP2005/022021 § 371(c)(1), (2), (4) Date Feb. 27, 2007, PCT Pub. No. WO2006/059660, PCT Pub. Date Jun. 08, 2006. |
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| Claims priority of application No. 2004-347312 (JP), filed on Nov. 30, 2004. | ||
| Prior Publication US 2007/0255700 A1, Nov. 01, 2007 | ||
| Int. Cl. G06F 13/14 (2006.01) | ||
| U.S. Cl. 710—305 [710/16; 710/33; 710/38; 710/107; 710/316] | 2 Claims |
| 1. A computer system, comprising:
a CPU;
a memory;
a peripheral device to which an address overlapping with a part of an address space assigned to the memory is assigned; and
a bus which connects the CPU to the peripheral device,
wherein the bus has a switch which switches a connection and a disconnection between the CPU and the memory;
wherein the CPU sends a signal indicating an address of an access destination to the bus when the CPU accesses either the
memory or the peripheral device; and
wherein the peripheral device includes:
an interface portion which receives the signal sent to the bus from the CPU and specifies the address indicated by the signal;
and
a decoding portion which controls the switch to disconnect a connection between the memory and the CPU when the address specified
by the interface portion is the address assigned to the peripheral device.
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