	US 7,487,264 B2
	High performance IP processor
Ashish A. Pandya, 4318 Lafayette Dr., El Dorado Hills, Calif. 95762 (US)
Filed on Jun. 10, 2003, as Appl. No. 10/459,297.
Claims priority of provisional application 60/388407, filed on Jun. 11, 2002.
Prior Publication US 2004/0030757 A1, Feb. 12, 2004
Int. Cl. G06F 15/16 (2006.01)

U.S. Cl. 709—250

22 Claims

1. An Internet Protocol (IP) processor system for enabling Transmission Control Protocol (TCP) or Stream Control Transmission Protocol (SCTP), or User Datagram Protocol (UDP), or other session oriented protocols over IP networks, said IP processor system comprising:

a. a plurality of packet processors for processing a plurality of packets including a first packet and a second packet, wherein the first packet and the second packet each have a connection ID associated therewith;

b. a session memory for storing IP session information related to the packets;

c. at least one memory controller for controlling memory accesses, wherein the memory accesses are performed to obtain session information of the packets;

d. at least one media interface for coupling to at least one network, wherein the packets are communicated via the at least one network;

e. a host interface configured to communicate a command to said IP processor system, and coupled to at least one host or a fabric interface coupled to a fabric; and

f. a scheduler configured to assign the first packet to one of the packet processors executing the second packet based on at least the connection ID associated with each of the first packet and the second packet.