| US 7,486,921 B2 | ||
| Method of producing electronic circuit, and electronic circuit substrate | ||
| Naoko Yamaguchi, Yokohama (Japan); Hideo Aoki, Yokohama (Japan); and Chiaki Takubo, Tokyo (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Dec. 22, 2004, as Appl. No. 11/17,922. | ||
| Claims priority of application No. P2003-435756 (JP), filed on Dec. 26, 2003. | ||
| Prior Publication US 2005/0153220 A1, Jul. 14, 2005 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G03G 15/20 (2006.01) | ||
| U.S. Cl. 399—320 [430/124.1] | 9 Claims |
| 1. A method of producing an electronic circuit, comprising:
forming an integrated resin layer made of B-stage solid resin at room temperature, containing no metal particle and having
a prescribed thickness by repeating a resin layer forming process a number of times so that resin layers made of B-stage solid
resin at room temperature and containing no metal particle are layered to be integrated with all the resin layers on a substrate,
wherein said resin layer forming process comprises:
charging the surface of a photoconductor with no pattern;
forming an electrostatic latent image having a prescribed pattern on the surface of the charged photoconductor by means of
laser irradiation;
forming a visible image by electrostatically attaching charged particles composed of B-stage solid resin at room temperature
and containing no metal particle on the surface of said photoconductor on which said electrostatic latent image is formed;
transferring the visible image formed on the surface of the photoconductor and composed of the charged particles onto the
substrate; and
hardening said visible image transferred onto said substrate on said substrate to form the resin layer made of B-stage solid
resin at room temperature and containing no metal particle on said substrate.
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