| US 7,486,578 B2 | ||
| Test method for ferroelectric memory | ||
| Tadashi Miyakawa, Yokohama (Japan); and Daisaburo Takashima, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jul. 03, 2007, as Appl. No. 11/822,244. | ||
| Claims priority of application No. 2006-184238 (JP), filed on Jul. 04, 2006. | ||
| Prior Publication US 2008/0013361 A1, Jan. 17, 2008 | ||
| Int. Cl. G11C 29/00 (2006.01) | ||
| U.S. Cl. 365—201 [365/145] | 20 Claims |
| 1. A test method for a ferroelectric memory including a cell block that includes: a block select transistor arranged between
a bit line and a local bit line, which is turned on/off depending on a potential of a block select line; memory cells arranged
between the local bit line and a plate line, each of the memory cells contains a cell transistor and a ferroelectric capacitor
connected in series, and the cell transistor turned on/off depending on a potential of word lines; and a reset transistor
arranged between the local bit line and the plate line, which is turned on/off depending on a potential of a reset line, the
method comprising:
applying a potential that allows the cell transistors to be ON to the word lines;
applying a potential that allows the reset transistor to be OFF to the reset line;
applying a potential that allows the block select transistor to be ON to the block select line; and
applying a stress voltage between the bit line and the plate line.
|