| US 7,486,575 B2 | ||
| Semiconductor memories with block-dedicated programmable latency register | ||
| Chul Woo Park, Yongin-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd, Suwon-si (Korea, Republic of) | ||
| Filed on Apr. 20, 2006, as Appl. No. 11/407,024. | ||
| Claims priority of application No. 10-2005-0065437 (KR), filed on Jul. 19, 2005. | ||
| Prior Publication US 2007/0019481 A1, Jan. 25, 2007 | ||
| Int. Cl. G11C 7/00 (2006.01) | ||
| U.S. Cl. 365—193 [365/194; 365/230.08] | 39 Claims |
| 1. A semiconductor memory device, comprising:
at least one memory bank having a plurality of memory blocks to store data, the data stored in the memory blocks capable of
being read in response to a read command;
a control unit to generate a plurality of CL values and to dedicate the CL values to predetermined ones of the memory blocks
to be read; and
an output circuit to output the data in response to a read signal activated by the read command, wherein the output circuit
outputs the data from each of the memory blocks based on the dedicated CL values.
|