| US 7,486,544 B2 | ||
| Semiconductor integrated circuit device | ||
| Ryo Mori, Higashiyamato (Japan); Toshio Yamada, Kokubunji (Japan); and Tetsuya Muraya, Hamura (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan) | ||
| Filed on Jul. 17, 2007, as Appl. No. 11/826,636. | ||
| Application 11/826636 is a continuation of application No. 11/169800, filed on Jun. 30, 2005, granted, now 7,245,521. | ||
| Claims priority of application No. 2004-222823 (JP), filed on Jul. 30, 2004. | ||
| Prior Publication US 2008/0013368 A1, Jan. 17, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 11/00 (2006.01); G11C 5/14 (2006.01) | ||
| U.S. Cl. 365—156 [365/154; 365/189.09; 365/226] | 10 Claims |
| 1. A semiconductor integrated circuit device comprising:
a plurality of memory cells each comprised of a storage in which input and output terminals of two inverter circuits are cross-connected
and a selection MOSFET provided between said storage and complementary bit lines and whose gate is connected to a word line;
an address selection circuit for setting all of word lines to a non-selection level in a standby state where any of writing
and reading operations is not performed on said memory cell; and
a substrate bias switching circuit,
wherein in normal operation, said substrate bias switching circuit supplies a power source voltage to an N-type well in which
a P-channel MOSFET of a memory cell is formed, and
wherein in said standby state, said substrate bias switching circuit supplies to said N-type well a predetermined voltage
which is lower than said power source voltage and by which a PN junction between the N-type well and the source of the P-channel
MOSFET is not forward biased.
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