| US 7,486,142 B2 | ||
| Radio frequency power amplifying module with hetero junction bipolar transistor | ||
| Hirokazu Tsurumaki, Tokyo (Japan); Hiroyuki Nagai, Tokyo (Japan); Tomio Furuya, Tokyo (Japan); Yoshiaki Harasawa, Tokyo (Japan); and Makoto Tabei, Tokyo (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan) | ||
| Filed on Dec. 29, 2006, as Appl. No. 11/618,197. | ||
| Claims priority of application No. 2006-040080 (JP), filed on Feb. 17, 2006. | ||
| Prior Publication US 2007/0194852 A1, Aug. 23, 2007 | ||
| Int. Cl. H03G 3/30 (2006.01) | ||
| U.S. Cl. 330—285 [330/296; 330/307] | 9 Claims |
| 1. An RF power module comprising a compound semiconductor integrated circuit and a silicon semiconductor integrated circuit,
wherein the compound semiconductor integrated circuit includes an output hetero junction bipolar transistor as a power amplifying
transistor for outputting an RF transmission output signal and a reference hetero junction bipolar transistor which are formed
over a compound semiconductor chip by the same manufacturing process, the output hetero junction bipolar transistor operates
on a common emitter, the reference hetero junction bipolar transistor operates on an emitter, a reference current depending
on the value of grounded emitter current amplification factor of the emitter flows in the reference hetero junction bipolar
transistor,
wherein the silicon semiconductor integrated circuit includes a bias circuit for the hetero junction bipolar transistor over
a silicon semiconductor substrate, the bias circuit includes a first current mirror to which the reference current of the
reference hetero junction bipolar transistor flows as input current and which generates output bias current that increases
in response to decrease in the grounded emitter current amplification factor, and
wherein an external reference output terminal in which the reference current of the reference hetero junction bipolar transistor
of the compound semiconductor integrated circuit flows and an input terminal of the first current mirror of the bias circuit
of the silicon semiconductor integrated circuit are electrically connected to each other, and an output terminal of the first
current mirror of the bias circuit of the silicon semiconductor integrated circuit and an external terminal of the compound
semiconductor integrated circuit connected to the base of the output hetero junction bipolar transistor are electrically connected
to each other.
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