| US 7,486,113 B2 | ||
| Decoder circuit | ||
| Akira Masuo, Osaka (Japan); Norihiko Sumitani, Osaka (Japan); and Shigeo Houmura, Kyoto (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Dec. 14, 2006, as Appl. No. 11/638,370. | ||
| Claims priority of application No. 2005-362322 (JP), filed on Dec. 15, 2005. | ||
| Prior Publication US 2007/0139230 A1, Jun. 21, 2007 | ||
| Int. Cl. G11C 8/00 (2006.01); H03K 19/084 (2006.01) | ||
| U.S. Cl. 326—106 [326/105; 326/108] | 5 Claims |
| 1. A decoder circuit comprising:
first and second transistors connected in series between a first reference node and a second reference node; and
third and fourth transistors connected in series between a connection node between the first and second transistors and the
second reference node,
wherein the first transistor is connected between the second reference node and the second transistor and receives a first
signal at its gate,
the second transistor is connected between the first transistor and the first reference node and receives a second signal
corresponding to the first signal at its gate,
the third transistor is connected between the second reference node and the fourth transistor and receives a third signal
at its gate,
the fourth transistor is connected between the third transistor and the connection node and receives a fourth signal corresponding
to the third signal at its gate, and
the first, second and fourth transistors are of the same conductivity type, and
wherein the first transistor is composed of a plurality of transistors connected in series between the second reference node
and the second transistor, and
the plurality of transistors receive the first signal at their gates.
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