| US 7,485,935 B2 | ||
| Semiconductor memory device | ||
| Takashi Miki, Hyogo (Japan); and Yasuo Murakuki, Kyoto (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Apr. 23, 2007, as Appl. No. 11/790,009. | ||
| Claims priority of application No. 2006-121349 (JP), filed on Apr. 25, 2006. | ||
| Prior Publication US 2007/0247889 A1, Oct. 25, 2007 | ||
| Int. Cl. H01L 27/088 (2006.01) | ||
| U.S. Cl. 257—390 [257/295; 257/751] | 12 Claims |
| 1. A semiconductor memory device comprising:
plural memory cells which are formed on a substrate and arranged in a matrix pattern, each memory cell having a capacitor;
plural bit lines, each bit line being commonly connected to the plural memory cells that are arranged in the same row;
plural word lines and plural plate lines, each word line and each plate line being commonly connected to the plural memory
cells that are arranged in the same column;
plural plate voltage supply lines arranged in the column direction; and
means for electrically connecting each of the plural plate voltage supply lines to each of the corresponding plural plate
lines;
wherein the plate voltage supply lines are composed of a material having a resistance lower than that of the plate lines;
each of the plural capacitors is covered with a hydrogen barrier film at its periphery;
the plural plate voltage supply lines are disposed beneath the hydrogen barrier film; and
the plural plate voltage supply lines are, when viewed in a plane, electrically connected to the same plate line at plural
positions of the same plate line, within a region where the hydrogen barrier film is disposed.
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