a semiconductor substrate having a first device area and a second device area;

a gate layer formed across the first device area and the second device area on the semiconductor substrate, wherein a first portion of the gate layer running across the first device area is doped with impurities of a first type, and a second portion of the gate layer running across the second device area is doped with impurities of a second type;

one or more source/drain doped regions at two sides of the gate layer;

one or more spacers formed on sidewalls of the gate layer;

a cap layer formed on the gate layer for protecting the same that is covered thereunder from forming a silicide structure, the cap layer having a first opening at a junction of the first and second portions of the gate layer and a second opening at another portion of the gate layer for interconnections between the gate layer and an overlying conductive layer;

one or more vias formed on the source/drain doped regions; and

a silicide layer formed on the source/drain doped regions and on the gate layer that is exposed by the first opening and the second opening, wherein the overlying conductive layer is connected to the silicide layer formed on the source/drain doped regions and the gate layer exposed by the second opening.