| US 7,485,930 B2 | ||
| Method for four direction low capacitance ESD protection | ||
| Jian-Hsing Lee, Hsin-Chu (Taiwan); and Shui-Hunyi Chen, Hsinchu (Taiwan) | ||
| Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (Taiwan) | ||
| Filed on Jan. 12, 2007, as Appl. No. 11/622,574. | ||
| Application 11/622574 is a division of application No. 10/207545, filed on Jul. 29, 2002, granted, now 7,179,691. | ||
| Prior Publication US 2007/0108527 A1, May 17, 2007 | ||
| Int. Cl. H01L 23/62 (2006.01) | ||
| U.S. Cl. 257—355 [257/E29.024] | 12 Claims |
| 1. A low capacitance device structure with associated parasitic bipolar transistor on a substrate for the purpose of providing
four-way electrostatic voltage discharge protection to a plurality of active semiconductor devices connected to an I/O logic
circuit line and including ESD protection of a power bus system comprising:
isolation elements defining an active circuit area;
a first and second FET gate element upon said substrate surface;
a plurality of first, second and third doped regions of opposite dopant than said substrate, wherein said plurality of first
doped regions form a source element and a drain element for said first FET gate element forming a first NFET device and said
plurality of second doped regions form a source region and a drain region for said second FET gate element forming a second
NFET device;
a plurality of fourth and fifth doped regions within said substrate of similar dopant as said substrate;
an electrical connection system for said first, second, third, fourth and fifth doped regions;
a surface passivation layer for said ESD protection device.
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