| US 7,485,923 B2 | ||
| SOI semiconductor device with improved halo region and manufacturing method of the same | ||
| Hisashi Takemura, Tokyo (Japan); Risho Koh, Tokyo (Japan); Yukishige Saito, Tokyo (Japan); and Jyonu Ri, Tokyo (Japan) | ||
| Assigned to NEC Corporation, Tokyo (Japan) | ||
| Appl. No. 10/490,599 PCT Filed Oct. 02, 2002, PCT No. PCT/JP02/10289 § 371(c)(1), (2), (4) Date Mar. 25, 2004, PCT Pub. No. WO03/032401, PCT Pub. Date Apr. 17, 2003. |
||
| Claims priority of application No. 2001-306543 (JP), filed on Oct. 02, 2001. | ||
| Prior Publication US 2005/0151172 A1, Jul. 14, 2005 | ||
| Int. Cl. H01L 29/772 (2006.01) | ||
| U.S. Cl. 257—336 [257/327; 257/335; 257/347; 257/E21.618; 257/E21.633] | 13 Claims |
| 1. A semiconductor device comprising:
a first insulating layer;
a semiconductor layer formed on said first insulating layer;
a second insulating layer on a part of said semiconductor layer; and
a gate electrode formed on said semiconductor layer through said second insulating layer,
wherein said semiconductor layer comprises:
a low concentration region formed under said gate electrode and said second insulating layer;
two diagonally or obliquely implanted high concentration regions formed in at least two regions on outer sides of said low
concentration region, substantially all of said high concentration regions being under said gate electrode and said second
insulating layer, and having an impurity concentration higher than that of said low concentration region, respectively; and
two source/drain regions formed in side portions outside said high concentration regions to have low concentration region
side end portions, respectively, and
a width of said high concentration regions is between 20 nm and 30 nm.
|