| US 7,485,921 B2 | ||
| Trench gate type MOS transistor semiconductor device | ||
| Yusuke Kawaguchi, Miura-gun (Japan); Yoshihiro Yamaguchi, Saitama (Japan); Syotaro Ono, Yokohama (Japan); and Miwako Akiyama, Hachioji (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Feb. 13, 2007, as Appl. No. 11/674,337. | ||
| Claims priority of application No. 2006-041954 (JP), filed on Feb. 20, 2006. | ||
| Prior Publication US 2007/0194375 A1, Aug. 23, 2007 | ||
| Int. Cl. H01L 29/78 (2006.01) | ||
| U.S. Cl. 257—331 [257/129; 257/139; 257/144; 257/152; 257/333; 257/341; 257/409; 257/E21.384; 257/E29.021; 257/E29.201; 438/242; 438/243] | 8 Claims |
| 1. A semiconductor device comprising:
a first semiconductor layer of a first conductivity type;
an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer;
a base layer of a second conductivity type formed on the surface of the epitaxial layer;
column layers of a second conductivity type repeatedly formed in the epitaxial layer under the base layer at a certain interval;
a diffusion layer of a first conductivity type formed selectively in the base layer; trenches formed so as to penetrate the
base layer to reach the epitaxial layer;
gate electrodes formed in the trenches via a gate insulation film formed on an inner wall of the trench;
a first main electrode connected to the back side of the first semiconductor layer;
a second main electrode connected to the diffusion layer and the base layer; and
a termination layer of a second conductivity type formed on the epitaxial layer at an end region at the perimeter of the base
layer, the termination layer being formed to have a junction depth larger than that of the base layer, impurity concentration
of the termination layer being set lower than the impurity concentration of the column layer,
wherein the column layers are formed exclusively under the base layer.
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