| US 7,485,913 B2 | ||
| Semiconductor memory device and method for fabricating the same | ||
| Hisashi Ogawa, Osaka (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Sep. 21, 2005, as Appl. No. 11/230,638. | ||
| Claims priority of application No. 2005-015562 (JP), filed on Jan. 24, 2005. | ||
| Prior Publication US 2006/0163639 A1, Jul. 27, 2006 | ||
| Int. Cl. H01L 27/108 (2006.01); H01L 29/94 (2006.01) | ||
| U.S. Cl. 257—308 [257/296; 257/306; 257/307; 257/310; 257/E27.084; 257/E27.087] | 16 Claims |
| 1. A semiconductor memory device comprising:
a memory cell including a first capacitor and a memory cell transistor, the first capacitor being composed of a first lower
electrode, a first capacitive insulating film and a first upper electrode, and the memory cell transistor including a first
gate electrode and a first doped layer; and
a dummy cell including a second capacitor and a dummy cell transistor, the second capacitor being composed of a second lower
electrode, a second capacitive insulating film and a second upper electrode, and the dummy cell transistor including a second
gate electrode and a second doped layer,
wherein the first upper electrode and the second upper electrode are formed from a same conductive film,
the first lower electrode is electrically connected to the first doped layer via a first contact plug directly connected to
the first lower electrode,
the second lower electrode is electrically connected to the second doped layer via a second contact plug directly connected
to the second lower electrode, and
the transverse dimension of the bottom of the second lower electrode being rectangular in planer shape is shorter than the
transverse dimension of the bottom of the first lower electrode being rectangular in planer shape.
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