| US 7,485,563 B2 | ||
| Method of providing solder bumps of mixed sizes on a substrate using a sorting mask and bumped substrate formed according to the method | ||
| Mengzhi Pang, Phoenix, Ariz. (US); and John Guzek, Chandler, Ariz. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Jun. 29, 2006, as Appl. No. 11/478,751. | ||
| Prior Publication US 2008/0003802 A1, Jan. 03, 2008 | ||
| Int. Cl. H01L 21/44 (2006.01) | ||
| U.S. Cl. 438—613 [438/612; 257/738; 257/779; 257/780] | 11 Claims |
| 1. A method of providing electrically conductive bumps on electrode pads of a microelectronic substrate comprising:
providing a microelectronic substrate including electrode pads thereon;
providing a sorting mask defining first openings and second openings therethrough, the second openings being larger than the
first openings;
disposing the mask onto the substrate such that the first openings and second openings register with respective ones of the
electrodes pads;
providing first solder portions onto corresponding ones of the electrode pads through the first openings, and second solder
portions onto corresponding ones of the electrode pads through the second openings, the second solder portions being larger
than the first solder portions and too large to be provided through the first openings, wherein the second solder portions
are provided through the second openings prior to providing the first solder portions through the first openings;
reflowing the first solder portions and second solder portions to form, respectively, first solder bumps and second solder
bumps on respective ones of the electrode pads; and
removing the mask after providing solder portions and before reflowing.
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