| US 7,485,537 B2 | ||
| Method of fabricating a vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness | ||
| Herbert L. Ho, New Windsor, N.Y. (US); Mahender Kumar, Fishkill, N.Y. (US); Qiqing Ouyang, Yorktown Heights, N.Y. (US); Paul A. Papworth, Wappingers Falls, N.Y. (US); Christopher D. Sheraw, Wappingers Falls, N.Y. (US); and Michael D. Steigerwalt, Newburgh, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Jul. 20, 2006, as Appl. No. 11/490,326. | ||
| Application 11/490326 is a division of application No. 10/931855, filed on Sep. 01, 2004, granted, now 7,115,965. | ||
| Prior Publication US 2006/0263993 A1, Nov. 23, 2006 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 21/331 (2006.01); H01L 21/8222 (2006.01); H01L 21/76 (2006.01) | ||
| U.S. Cl. 438—309 [438/311; 438/312; 438/313; 438/342] | 1 Claim |

| 1. A method of fabricating a bipolar transistor comprising:
providing a silicon-on-insulator (SOI) substrate comprising a first semiconductor layer containing a first conductivity type
dopant located over a first buried insulating layer, wherein a portion of the first buried insulating layer beneath said first
semiconductor layer is removed by forming a trench into the first semiconductor layer, stopping on said first insulating layer,
and performing an isotropic etch process to form an undercut region;
forming a second buried insulating layer on exposed surfaces of said first semiconductor layer, wherein said second buried
insulating layer is thinner than said first buried insulating layer and is formed by a thermal growth process;
filling the undercut region and the removed portion of the first semiconductor layer with a conductive back electrode material
comprised of doped polysilicon;
forming a base utilizing an epitaxial growth process, said base comprising a second semiconductor layer containing a second
conductivity type dopant that is different than the first conductivity type dopant;
forming an emitter comprising a third semiconductor layer including said first conductivity type dopant over a portion of
said base; and
biasing the conductive back electrode material to form an accumulation layer at an interface between the first semiconductor
layer and the second buried insulating layer.
|