| US 7,485,503 B2 | ||
| Dielectric interface for group III-V semiconductor device | ||
| Justin K. Brask, Portland, Oreg. (US); Suman Datta, Beaverton, Oreg. (US); Mark L. Doczy, Beaverton, Oreg. (US); James M. Blackwell, Portland, Oreg. (US); Matthew V. Metz, Hillsboro, Oreg. (US); Jack T. Kavalieros, Portland, Oreg. (US); and Robert S. Chau, Beaverton, Oreg. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Nov. 30, 2005, as Appl. No. 11/292,399. | ||
| Prior Publication US 2007/0123003 A1, May 31, 2007 | ||
| Int. Cl. H01L 21/335 (2006.01); H01L 21/338 (2006.01); H01L 27/108 (2006.01) | ||
| U.S. Cl. 438—142 [438/172; 257/183; 257/310; 257/E31.019; 257/E31.033] | 13 Claims |
| 1. A method for fabricating a semiconductor device comprising:
growing a first region of a Group III-V compound;
growing a confinement region on the first region;
forming a chalcogenide region on the confinement region;
forming a dielectric region on the chalcogenide region, wherein the chalco enide re ion corn rises an [ο]n bridge between the confinement re ion and the dielectric region, where n is greater than 1; and
forming a metal gate on the dielectric region.
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