| US 7,484,193 B2 | ||
| Method and software for predicting the timing delay of a circuit path using two different timing models | ||
| Aveek Sarkar, Mountain View, Calif. (US); Shian-Jiun Fu, Sunnyvale, Calif. (US); Peter Lai, San Jose, Calif. (US); and Rambabu Pyapali, Cupertino, Calif. (US) | ||
| Assigned to Sun Microsystems, Inc., Santa Clara, Calif. (US) | ||
| Filed on Aug. 28, 2003, as Appl. No. 10/651,113. | ||
| Prior Publication US 2005/0050405 A1, Mar. 03, 2005 | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—6 [716/1] | 35 Claims |
| 1. A method for predicting a timing response of a circuit path, the method comprising:
receiving a circuit block netlist;
obtaining a first estimated timing response of a first circuit path of said circuit block netlist using a first timing model;
obtaining a second estimated timing response of the first circuit path of said circuit block netlist using a second timing
model;
generating a correction factor based on a variation between the first estimated timing response and the second estimated timing
response, wherein generating a correction factor includes determining a statistical variation between the first estimated
timing response and the second estimated timing response; and
applying the correction factor to the first timing model.
|