| US 7,484,154 B2 | ||
| Semiconductor integrated circuit, method for testing semiconductor integrated circuit, and computer readable medium for the same | ||
| Koji Urata, Saitama (Japan); and Yasutomo Onozaki, Chiba (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jul. 06, 2006, as Appl. No. 11/480,958. | ||
| Claims priority of application No. 2005-197888 (JP), filed on Jul. 06, 2005. | ||
| Prior Publication US 2007/0022343 A1, Jan. 25, 2007 | ||
| Int. Cl. G01R 31/28 (2006.01) | ||
| U.S. Cl. 714—733 [714/718; 714/729] | 5 Claims |
| 1. A semiconductor integrated circuit comprising:
a random access memory;
a memory BIST circuit that writes a memory test pattern into the random access memory after the random access memory passes
a failure test;
a scan chain which effects shift-in of a logic test pattern generated by automatic pattern generation on condition that the
memory test pattern is read without being rewritten; and
a combinational logic circuit that can configure a system logic circuit along with the scan chain, wherein
the random access memory outputs a data signal read from the memory test pattern, by a read command signal that is attributable
to the logic test pattern and is passed the combinational logic circuit,
a test result that is attributed to the-read data signal and is passed through the combinational logic circuit is input to
the scan chain, and
the scan chain shifts out the test result.
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