| US 7,484,153 B2 | ||
| Systems and methods for LBIST testing using isolatable scan chains | ||
| Naoki Kiryu, Tokyo (Japan); Mack Wayne Riley, Austin, Tex. (US); and Nathan Paul Chelstrom, Austin, Tex. (US) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan); and International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Dec. 06, 2005, as Appl. No. 11/295,057. | ||
| Prior Publication US 2007/0130489 A1, Jun. 07, 2007 | ||
| Int. Cl. G01R 31/28 (2006.01) | ||
| U.S. Cl. 714—733 [714/727] | 8 Claims |
| 1. A method for isolating logic built-in self-test (LBIST) circuitry in a device comprising:
providing a plurality of scan chains interposed with functional logic of the device, wherein each of a plurality of functional
blocks in the device has a corresponding set of scan chains interposed therewith, and wherein the set of scan chains corresponding
to each functional block includes one or more boundary scan chain that is selectively coupled to one or more boundary scan
chains of other functional blocks; and
selectively coupling or decoupling the boundary scan chains of each functional block with the boundary scan chains of other
functional blocks;
wherein the boundary scan chains in the processor cores and supporting functional blocks are selectively coupled to the boundary
scan chains in other processor cores and supporting functional blocks through AND gates, wherein the coupling the boundary
scan chains comprises asserting a control input to the AND gates, wherein the decoupling the boundary scan chains comprises
deasserting the control input to the AND gates, and wherein the asserting or the deasserting the control input to each AND
gate comprises loading a corresponding value in a control latch, wherein an output of the control latch is coupled to an input
of the AND gate.
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