| US 7,484,152 B2 | ||
| Securing the test mode of an integrated circuit | ||
| Frederic Bancel, Lamanon (France); and David Hely, Les Pennes Mirabeau (France) | ||
| Assigned to STMicoelectronics SA, Montrouge (France) | ||
| Filed on Feb. 08, 2006, as Appl. No. 11/351,344. | ||
| Claims priority of application No. 05 01266 (FR), filed on Feb. 08, 2005. | ||
| Prior Publication US 2006/0195723 A1, Aug. 31, 2006 | ||
| Int. Cl. G01R 31/28 (2006.01) | ||
| U.S. Cl. 714—730 | 20 Claims |
| 1. An electronic circuit, comprising:
a logic circuit comprising a plurality of logic units;
a plurality of memory units of a shift register connected to the plurality of logic units, and having reception terminals
for reception of command signals;
an access controller having a plurality of outputs connected to the reception terminals of the plurality of memory units and
applying the command signals to the outputs; and
a scrutinizing module measuring at least one command signal between an output of the access controller and a reception terminal
of a memory unit, determining if the measured signal differs from the command signal applied to the output of the access controller,
and blocking formation of the shift register.
|