| US 7,484,151 B2 | ||
| Method and apparatus for testing logic circuit designs | ||
| Kedarnath Balakrishnan, Princeton, N.J. (US); Seongmoon Wang, Plainsboro, N.J. (US); Wenlong Wei, Mercerville, N.J. (US); and Srimat T. Chakradhar, Manalapan, N.J. (US) | ||
| Assigned to NEC Laboratories America, Inc., Princeton, N.J. (US) | ||
| Filed on Oct. 03, 2006, as Appl. No. 11/538,245. | ||
| Claims priority of provisional application 60/743487, filed on Mar. 15, 2006. | ||
| Claims priority of provisional application 60/743359, filed on Feb. 27, 2006. | ||
| Claims priority of provisional application 60/723036, filed on Oct. 03, 2005. | ||
| Prior Publication US 2007/0113129 A1, May 17, 2007 | ||
| Int. Cl. G01R 31/28 (2006.01) | ||
| U.S. Cl. 714—728 [714/738; 714/739; 714/726] | 8 Claims |
| 1. A logic testing system comprising:
a decompressor;
a tester in communication with said decompressor, said tester configured to store a seed and locations of scan inputs and
further configured to transmit said seed and said locations of scan inputs to said decompressor,
said decompressor configured to generate a test pattern from said seed and said locations of scan inputs, said decompressor
comprising:
a first test pattern generator configured to generate a random test pattern,
a second test pattern generator configured to generate a deterministic test pattern from said seed, and
a selector configured to select one of said random test pattern and said deterministic test pattern using said locations of
scan inputs.
|