| US 7,484,144 B2 | ||
| Testing embedded memory in an integrated circuit | ||
| Wei Han, Beaverton, Oreg. (US); and Loren McLaury, Hillsboro, Oreg. (US) | ||
| Assigned to Lattice Semiconductor Corporation, Hillsboro, Oreg. (US) | ||
| Filed on Aug. 30, 2004, as Appl. No. 10/929,199. | ||
| Prior Publication US 2006/0059386 A1, Mar. 16, 2006 | ||
| Int. Cl. G11C 29/00 (2006.01); G11C 7/00 (2006.01); G06F 11/00 (2006.01) | ||
| U.S. Cl. 714—719 [714/735; 365/201] | 14 Claims |
| 1. An integrated circuit, comprising:
a first bus;
at least one array of embedded memories;
a bidirectional data bus coupled to the array of embedded memories and to the first bus such that test vectors may be written
from the first bus to selected embedded memories in the array through the bidirectional data bus;
a test circuit adapted to compare test vectors on the first bus to test vectors read back from the selected embedded memories
in the array through the bidirectional data bus to provide a comparison result; and
a tri-state buffer coupled between the first bus and the bidirectional bus, the tri-state buffer adapted to being driven into
a high-impedance mode while test vectors are read back from the embedded memories.
|