| US 7,484,045 B2 | ||
| Store performance in strongly-ordered microprocessor architecture | ||
| Vladimir Pentkovksi, Folsom, Calif. (US); Ling Cen, Austin, Tex. (US); Vivek Garg, Folsom, Calif. (US); Deep Buch, Folsom, Calif. (US); and David Zhao, Pinole, Calif. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Mar. 30, 2004, as Appl. No. 10/813,942. | ||
| Prior Publication US 2005/0223177 A1, Oct. 06, 2005 | ||
| Int. Cl. G06F 12/08 (2006.01) | ||
| U.S. Cl. 711—145 [711/152] | 24 Claims |
| 1. A processor having a strong ordering instruction architecture comprising:
a store buffer from which a second data value is to be read and stored to a cache memory regardless of whether a first data
value that is to be read from the store buffer prior to the second data value being read from the store buffer has been globally
observable; and
a global observation store buffer (GoSB) to store only the first and second data values after they have become globally observable,
wherein the GoSB comprises an index field for each data value to be stored within the GoSB.
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