| US 7,484,041 B2 | ||
| Systems and methods for loading data into the cache of one processor to improve performance of another processor in a multiprocessor system | ||
| Takashi Yoshikawa, Kawasaki (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Apr. 04, 2005, as Appl. No. 11/98,109. | ||
| Prior Publication US 2006/0224831 A1, Oct. 05, 2006 | ||
| Int. Cl. G06F 9/38 (2006.01) | ||
| U.S. Cl. 711—137 [711/130; 711/213; 712/207] | 20 Claims |
| 1. A system comprising:
a plurality of processors, each of which has a corresponding cache memory; and
a bus coupled to each of the processors;
wherein at least a first one of the processors is configured to issue a preload command to the bus, wherein the preload command
directs a target one of the processors which is different from the first one of the processors to load data into the cache
memory corresponding to the target processor;
wherein the first one of the processors is configured to issue the preload command in response to data being cast out of the
cache memory corresponding to the first processor, wherein the data cast out of the cache memory corresponding to the first
processor is the data preloaded into the cache memory corresponding to the target processor; and
wherein the first one of the processors is configured to retrieve the data preloaded into the cache memory corresponding to
the target processor and to perform an operation on the data retrieved from the cache memory corresponding to the target processor.
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