| US 7,483,299 B2 | ||
| Devices and operation methods for reducing second bit effect in memory device | ||
| Tzu-Hsuan Hsu, Jhongpu Township, Chiayi County (Taiwan); Chao-I Wu, Zhubei (Taiwan); and Erh-Kun Lai, Taichung County (Taiwan) | ||
| Assigned to Macronix International Co., Ltd., Hsinchu (Taiwan) | ||
| Filed on Aug. 01, 2006, as Appl. No. 11/496,441. | ||
| Prior Publication US 2008/0031039 A1, Feb. 07, 2008 | ||
| Int. Cl. G11C 11/03 (2006.01) | ||
| U.S. Cl. 365—185.1 [365/185.18; 365/185.26; 365/185.27] | 24 Claims |
| 1. A semiconductor memory device, comprising:
a substrate having a first conductivity type;
a first region provided in the substrate, the first region having a second conductivity type;
a second region provided in the substrate spaced from the first region, the second region having the second conductivity type;
a channel region provided in the substrate and extending between the first and second regions;
a first insulative layer including a first material provided on the channel region;
a second insulative layer including a second material provided on the first insulative layer, the second insulative layer
being configured to store a first charge in a first portion corresponding to a first bit and a second charge in a second portion
corresponding to a second bit;
a third insulative layer provided on the second insulative layer;
a first conductive layer provided on the third insulative layer;
a fourth insulative layer provided on the first conductive layer; and
a second conductive layer provided on the fourth insulative layer.
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