| US 7,482,851 B2 | ||
| Latch and clock structures for enabling race-reduced mux scan and LSSD co-compatibility | ||
| David E. Lackey, Jericho, Vt. (US); Steven F. Oakland, Colchester, Vt. (US); and Peter Verwegen, Rottenburg, Del. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Jun. 18, 2007, as Appl. No. 11/764,610. | ||
| Application 11/764610 is a division of application No. 11/082990, filed on Mar. 18, 2005. | ||
| Prior Publication US 2008/0042712 A1, Feb. 21, 2008 | ||
| Int. Cl. H03K 3/289 (2006.01) | ||
| U.S. Cl. 327—202 [327/203; 714/726] | 11 Claims |
| 1. An edge triggered system having a data and scan input, comprising:
a latch device having a clock input; and
an AND gate, coupled to said latch device, structured and arranged to receive a first clock signal and an inverted clock signal
to generate a clock to said clock input,
wherein the latch device and the AND gate are configured to provide mux-scan and LSSD testing capabilities, and
further comprising a mux coupled to a data input and a scan input, wherein
said latch device comprises at least a first and second latch, in which each latch has a clock input,
said AND gate is coupled to said first latch, and a second clock signal is coupled to said clock input of said second latch,
and
a third clock signal, formed from the second clock signal, is coupled to said AND gate to form the inverted clock signal.
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