| US 7,482,828 B2 | ||
| Methods and apparatus for device testing at the wafer level | ||
| Andre Richard Lalonde, Allen, Tex. (US); James Kenneth Guenter, Garland, Tex. (US); and R. Stephen Speer, Sachse, Tex. (US) | ||
| Assigned to Finisar Corporation, Sunnyvale, Calif. (US) | ||
| Filed on Jul. 13, 2006, as Appl. No. 11/457,412. | ||
| Claims priority of provisional application 60/698890, filed on Jul. 13, 2005. | ||
| Prior Publication US 2007/0013400 A1, Jan. 18, 2007 | ||
| Int. Cl. G01R 31/26 (2006.01) | ||
| U.S. Cl. 324—765 | 22 Claims |
| 1. A method of testing one or more devices at a wafer level, the method comprising:
generating a test signal;
supplying the test signal to a single device on a wafer;
providing an output of the single device to each of a plurality of devices on the wafer by way of a common electrical connection
between the single device and the plurality of devices;
providing an output of each of the plurality of devices to a corresponding return connection by way of electrical connections
between the plurality of devices and the plurality of return connections; and
receiving return currents from each of the return connections.
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