| US 7,482,695 B2 | ||
| Stack MCP and manufacturing method thereof | ||
| Shinya Takyu, Kitakatsushika-gun (Japan); Kazuhiro Iizuka, Yokohama (Japan); and Mika Kiritani, Kawasaki (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jul. 13, 2007, as Appl. No. 11/826,286. | ||
| Application 11/826286 is a division of application No. 10/891513, filed on Jul. 15, 2004, granted, now 7,285,864. | ||
| Claims priority of application No. 2004-036446 (JP), filed on Feb. 13, 2004. | ||
| Prior Publication US 2007/0262445 A1, Nov. 15, 2007 | ||
| Int. Cl. H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01) | ||
| U.S. Cl. 257—777 [257/738; 257/E23.021; 257/E27.137; 257/E27.144; 257/E27.161] | 4 Claims |
| 1. A semiconductor device comprising:
a plurality of semiconductor chips stacked and packaged, at least one of the plurality of semiconductor chips including:
an adhesive layer formed on an entire surface of an element-forming surface of the semiconductor chip;
a bump formed on a pad on the semiconductor chip and in the adhesive layer, the bump projecting from the adhesive layer; and
a bonding wire which is bonded to a projecting portion of the bump, the bonding wire electrically connecting the bump to a
wiring layer formed on a printed circuit board,
wherein a semiconductor chip of the plurality of semiconductor chips which is arranged in an upper stage is smaller than a
semiconductor chip of the plurality of semiconductor chip which is arranged in a lower stage, and
wherein said at least one semiconductor chip includes a semiconductor chip having substantially a same size as the semiconductor
chip of the lower stage, said device further comprising:
a spacer smaller than the plurality of semiconductor chips and interposed between the semiconductor chips having substantially
the same size; and
a fillet provided between the spacer and the semiconductor chips and covering a connection between the bump and the bonding
wire.
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