| US 7,482,661 B2 | ||
| Pattern forming method and semiconductor device manufactured by using said pattern forming method | ||
| Toshiya Kotani, Sagamihara (Japan); Satoshi Tanaka, Kawasaki (Japan); and Soichi Inoue, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on May 03, 2005, as Appl. No. 11/119,810. | ||
| Application 11/119810 is a division of application No. 10/183572, filed on Jun. 28, 2002, granted, now 6,901,577. | ||
| Claims priority of application No. 2001-199647 (JP), filed on Jun. 29, 2001. | ||
| Prior Publication US 2005/0193364 A1, Sep. 01, 2005 | ||
| Int. Cl. H01L 27/088 (2006.01) | ||
| U.S. Cl. 257—401 [257/499; 257/503; 257/E23.141; 257/E23.142; 257/E23.151; 438/183; 438/926] | 20 Claims |
| 1. A semiconductor device comprising:
a first gate wiring pattern formed on a first element region;
a second gate wiring pattern formed on a second element region different from said first element region and arranged with
a first space with respect to said first gate wiring pattern;
a wiring pattern arranged between said first and second gate wiring patterns and formed on an element isolation region disposed
between said first and second element regions;
a third gate wiring pattern formed on a third element region different from said first and second element regions;
a fourth gate wiring pattern formed on a fourth element region different from said first to third element regions and arranged
with a second space with respect to said third gate wiring pattern, said second space being smaller than said first space,
said first to fourth gate wiring patterns and said wiring pattern being formed from a same layer;
a contact arranged on said wiring pattern and electrically connected to the wiring pattern; and
a metal layer arranged above said wiring pattern and connected to said contact to fix a potential of said wiring pattern.
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