	US 7,482,221 B2
	Memory device and method of manufacturing a memory device
Klaus Muemmler, Dresden (Germany); Stefan Tegen, Dresden (Germany); Peter Baars, Dresden (Germany); and Joern Regul, Dresden (Germany)
Assigned to Infineon Technologies AG, Munich (Germany)
Filed on Aug. 15, 2005, as Appl. No. 11/203,927.
Prior Publication US 2007/0037334 A1, Feb. 15, 2007
Int. Cl. H01L 21/8242 (2006.01)

U.S. Cl. 438—241 [438/253; 438/255; 438/256]

8 Claims

1. A method of forming an integrated circuit comprising a plurality of storage capacitors, the method comprising:

providing a sacrificial layer covering a substrate surface of a semiconductor substrate;

defining openings in the sacrificial layer, each opening exposing an array contact pad formed in an array portion of the semiconductor substrate;

defining peripheral contact openings in the sacrificial layer, each peripheral contact opening exposing a part of a peripheral circuitry formed in a peripheral portion of the semiconductor substrate;

thereafter providing a storage electrode of a first conductive material in each of the openings in the array portion so that each storage electrode is in contact with one of the array contact pads;

masking the peripheral portion with a layer of a second masking material which is different from a material of the sacrificial layer;

removing the sacrificial layer from the array portion while maintaining the sacrificial layer in the peripheral portion;

providing a storage dielectric on each storage electrode;

thereafter removing the second masking material; and

thereafter providing a counter electrode on each storage dielectric in the array portion thereby completing the plurality of storage capacitors and a second conductive material in the peripheral contact openings so as to complete a plurality of peripheral contacts.