| US 7,482,206 B2 | ||
| Semiconductor devices having nano-line channels and methods of fabricating the same | ||
| Seung-Jae Baik, Seoul (Korea, Republic of); In-Seok Yeo, Seoul (Korea, Republic of); Sang-Sig Kim, Seoul (Korea, Republic of); Ki-Hyun Kim, Seoul (Korea, Republic of); and Dong-Young Jeong, Seoul (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Jun. 07, 2006, as Appl. No. 11/422,663. | ||
| Claims priority of application No. 10-2005-0048709 (KR), filed on Jun. 08, 2005; and application No. 10-2006-0021692 (KR), filed on Mar. 08, 2006. | ||
| Prior Publication US 2007/0072335 A1, Mar. 29, 2007 | ||
| Int. Cl. H01L 21/335 (2006.01) | ||
| U.S. Cl. 438—142 [438/216; 438/259; 438/270; 257/330; 257/388; 257/E51.007; 257/401] | 16 Claims |
| 1. A method of fabricating a semiconductor device comprising:
forming a sacrificial material layer on a substrate;
disposing at least one nano-line having semiconductor characteristics on the sacrificial material layer;
forming a mask pattern on a portion of the nano-line and the sacrificial material layer;
forming spaced apart source and drain electrodes at respective sides of the mask pattern and surrounding respective portions
of the nano-line at the respective sides of the mask pattern;
removing the mask pattern and at least a portion of the sacrificial material layer below the mask pattern and the at least
one nano-line to form an opening exposing a portion of the nano-line between the source and drain electrodes; and
forming a gate electrode surrounding the exposed portion of the nano-line.
|