| US 7,480,841 B2 | ||
| Semiconductor integrated circuit which properly executes an operational test of a circuit under test in the semiconductor integrated circuit | ||
| Yasukazu Kai, Miyazaki (Japan); and Yoshihiro Nakatake, Miyazaki (Japan) | ||
| Assigned to Oki Electric Industry Co., Ltd., Tokyo (Japan) | ||
| Filed on Dec. 28, 2007, as Appl. No. 11/965,790. | ||
| Application 11/965790 is a division of application No. 11/090293, filed on Mar. 28, 2005, granted, now 7,334,168, filed on Feb. 19, 2008. | ||
| Application 11/090293 is a continuation in part of application No. 10/990430, filed on Nov. 18, 2004, abandoned. | ||
| Claims priority of application No. 2004-109086 (JP), filed on Apr. 01, 2004. | ||
| Prior Publication US 2008/0126894 A1, May 29, 2008 | ||
| Int. Cl. G06F 11/25 (2006.01) | ||
| U.S. Cl. 714—724 | 12 Claims |
| 1. A semiconductor integrated circuit, operable normal operational mode and a test mode, comprising:
a plurality of external input terminals which receives a plurality of external signals;
a logic circuit coupled to the external input terminals, wherein the logic circuit outputs a plurality of internal input signals
based on the external signals;
a circuit under test (CUT) coupled to the logic circuit to receive the internal input signals, wherein the CUT generates an
internal output signal for the logic circuit when the semiconductor integrated circuit operates in the normal operational
mode;
an input switching circuit coupled between the logic circuit and the CUT, wherein the input switching circuit prohibits the
CUT from receiving the internal input signals when the semiconductor integrated circuit operates in the test mode;
a pseudo test terminal coupled to the CUT and the logic circuit, wherein a pseudo test signal is input to the logic circuit
through the pseudo test terminal when the CUT is prohibited from receiving the internal input signals.
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